发明名称 METHOD FOR FORMING METAL LINE IN SEMICONDUCTOR DEVICE
摘要 A method for forming a metal line of a semiconductor device is provided to reduce a wiring capacitance value by using a nitride layer instead of a Ti/TiN layer as a stopper. A first metal layer(102), a nitride layer(103), and an interlayer dielectric(104) are sequentially deposited on a semiconductor substrate(100) including a lower structure. A via hole is formed by etching a predetermined region of the interlayer dielectric, in order to expose the nitride layer. A first metal layer is exposed by etching the exposed nitride layer at a bottom surface of the via hole. A conductive material is deposited on an entire structure in order to bury the via hole. A contact(107) is formed within the via hole by performing a CMP(Chemical Mechanical Polishing) process. A second metal layer(108) is formed on the entire structure including the contact.
申请公布号 KR20080022384(A) 申请公布日期 2008.03.11
申请号 KR20060085741 申请日期 2006.09.06
申请人 HYNIX SEMICONDUCTOR INC. 发明人 KIM, SUK JOONG;JEONG, CHEOL MO;CHO, WHEE WON;MYUNG, SEONG HWAN
分类号 H01L21/28 主分类号 H01L21/28
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