发明名称 Vector interface to shared memory in simulating a circuit design
摘要 A first block, a second block, a shared memory, and a third block are generated in a circuit design in response to user input control. The first block is coupled to the second block, the second block is coupled to the shared memory, and the shared memory is coupled to the third block in response to user input control. During one cycle of a simulation, the second block, in response to the first block, accesses a set of scalar values in the shared memory using scalar accesses. During one cycle of the simulation, the set of scalar values is transferred between the second block and the first block. During the simulation, the shared memory is accessed by the third block using scalar accesses.
申请公布号 US7343572(B1) 申请公布日期 2008.03.11
申请号 US20050096024 申请日期 2005.03.31
申请人 XILINX, INC. 发明人 STONE JOSHUA IAN;BALLAGH JONATHAN B.;MILNE ROGER B.;SHIRAZI NABEEL
分类号 G06F17/50 主分类号 G06F17/50
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