发明名称 METHOD FOR CAPTURING AND USING DESIGN INTENT IN AN INTEGRATED CIRCUIT FABRICATION PROCESS
摘要 A method for capturing and using design intent within an IC fabrication process. The design intent information is produced along with the design release by a design company. The design release and design intent information are coupled to an IC manufacturing facility where the design release is used for producing the layout of the integrated circuit and the design intent information is coupled to the equipment, especially the metrology equipment, within the IC manufacturing facility. As such, the design intent information can be used to optimize processing during IC fabrication to achieve optimization of the critical characteristics intended by the designer.
申请公布号 US2008059261(A1) 申请公布日期 2008.03.06
申请号 US20070935030 申请日期 2007.11.05
申请人 MADOK JOHN H;YOST DENNIS J;CHEUNG BOBIN W 发明人 MADOK JOHN H.;YOST DENNIS J.;CHEUNG BOBIN W.
分类号 G06Q10/00;G06Q50/00;G06F17/50;H01L21/02;H01L21/82;H01L27/10 主分类号 G06Q10/00
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