发明名称 Method and system for combining page buffer list entries to optimize caching of translated addresses
摘要 Certain aspects of a method and system for combining page buffer list entries (PBLEs) to optimize caching of translated addresses are disclosed. Aspects of a method may include encoding at least two page buffer list entries in a remote direct memory access (RDMA) memory map into at least two contiguous memory locations by utilizing a remainder of a physical address corresponding to the two page buffer list entries. The first memory location of the two contiguous memory locations may comprise a base address and a contiguous length of the first page buffer list entry. The second memory location of the two contiguous memory locations may comprise a virtual address and a contiguous length of the second page buffer list entry.
申请公布号 US2008059600(A1) 申请公布日期 2008.03.06
申请号 US20060515563 申请日期 2006.09.05
申请人 BESTLER CAITLIN 发明人 BESTLER CAITLIN
分类号 G06F15/167;G06F15/16 主分类号 G06F15/167
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