| 摘要 |
A semiconductor memory apparatus includes a phase comparator configured to compare phases of rising and falling feedback clocks with that of a reference clock, a delay circuit configured to delay the reference clock by a predetermined time based on a comparison result of the phase comparator to thereby generate rising and falling delayed clocks, a clock transmission block configured to invert the rising delayed clock outputted from the delay circuit when the rising and falling feedback clocks have substantially different phases, a duty compensator configured to compensate a duty ratio from outputs of the clock transmitting block to generate a delay locked clock having a compensated duty ratio, and a delay model configured to delay an output and an inverse output of the duty compensator by a modeled delay time respectively to generate the rising and falling feedback clocks.
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