发明名称 TECHNIQUE FOR REDUCING PLASMA-INDUCED ETCH DAMAGE DURING THE FORMATION OF VIAS IN INTERLAYER DIELECTRICS
摘要 By forming a conductive material within an etch mask for an anisotropic etch process for patterning openings, such as vias, in a dielectric layer of a metallization structure, the probability for arcing events may be reduced, since excess charge may be laterally distributed. For example, an additional sacrificial conductive layer may be formed or an anti-reflecting coating (ARC) may be provided in the form of a conductive material in order to obtain the lateral charge distribution.
申请公布号 US2008057705(A1) 申请公布日期 2008.03.06
申请号 US20070696226 申请日期 2007.04.04
申请人 FEUSTEL FRANK;FROHBERG KAI;WERNER THOMAS 发明人 FEUSTEL FRANK;FROHBERG KAI;WERNER THOMAS
分类号 H01L21/4763 主分类号 H01L21/4763
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