| 摘要 |
PROBLEM TO BE SOLVED: To effectively prevent erroneous read-out caused by voltage rise of a storage node. SOLUTION: Each memory cell 1A constituting a memory cell array is provided with a write transistor WT, a storage node SN holding data input from the write transistor WT in an electrical floating state, and a read transistor (amplifier transistor AT) of which the gate is connected to the storage node SN and which outputs storage data from a source or a drain by being turned on or off in accordance with holding voltage of the storage node SN. Then, a boosting part (diode connection transistor DT) boosting voltage of the source or the drain from common voltage (ground voltage) is connected to a source or a drain opposite to an output side of the storage data of the amplifier transistor AT. COPYRIGHT: (C)2008,JPO&INPIT
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