| 摘要 |
A timing detection circuit including a first timing detection circuit, a second detection circuit, and an output circuit is disclosed. The first detection circuit detects, among multiphase clocks having n mutually different phases and a frequency of k times the frequency of a reference clock, a closest clock having a clock edge closest to a valid edge of the synchronizing signal and generates first detect signal DET_A indicating the detected clock. The second timing detection circuit detects within which of k successive cycles of the representative clock selected from the multiphase clocks the valid edge of the synchronizing signal is positioned and generates second detect signal DET_B indicating the detected cycle. The output circuit receives the first detect signal and the second detect signal and outputs first output signal OUT_A and second output signal OUT_B.
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