| 摘要 |
A clock switching circuit for switching between plural clock signals includes a selector for outputting a first control signal when a low speed clock is selected by a selection signal with a permission signal halted, and a second control signal when a high speed clock is selected by the selection signal with a second permission signal halted. The switching circuit includes a first stabilizer for holding the first control signal in timed with the low speed clock to output the second permission signal, and a second stabilizer for holding the second control signal in timed with the high speed clock to output the first permission signal. The switching circuit includes a first and a second gating cell circuit for latching and outputting the low speed clock and the high speed clock when the second permission signal and the first permission signal is supplied, respectively.
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