发明名称 |
Computer system and control method for controlling processor |
摘要 |
A processor reads a program including a prefetch command and a load command and data from a main memory, and executes the program. The processor includes: a processor core that executes the program; a L2 cache that stores data on the main memory for each predetermined unit of data storage; and a prefetch unit that pre-reads the data into the L2 cache from the main memory on the basis of a request for prefetch from the processor core. The prefetch unit includes: a L2 cache management table including an area in which a storage state is held for each position in the unit of data storage of the L2 cache and an area in which a request for prefetch is reserved; and a prefetch control unit that instructs, the L2 cache to perform the request for prefetch reserved or the request for prefetch from the processor core.
|
申请公布号 |
US2008059715(A1) |
申请公布日期 |
2008.03.06 |
申请号 |
US20070705410 |
申请日期 |
2007.02.13 |
申请人 |
TOMITA AKI;SUKEGAWA NAONOBU |
发明人 |
TOMITA AKI;SUKEGAWA NAONOBU |
分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|