发明名称 |
Reduction of punch-thru defects in damascene processing |
摘要 |
A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is formed over the substrate. A conductive trench is formed within the first dielectric layer. An etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over/on the etch stop layer. A resist mask is formed over the device and via openings are etched in the second dielectric layer. The resist mask is removed by an ash process. A clean process is performed that mitigates/reduces surface charge on exposed portions of the etch stop layer. Additional surface charge reduction techniques are employed. The via openings are filled with a conductive material and a planarization process is performed to remove excess fill material.
|
申请公布号 |
US2008057711(A1) |
申请公布日期 |
2008.03.06 |
申请号 |
US20060511698 |
申请日期 |
2006.08.29 |
申请人 |
TEXAS INSTRUMENTD INCORPORATED |
发明人 |
MATZ PHILLIP DANIEL;CHEVACHAROENKUL SOPA;LIN CHING-TE;CHATTERJEE BASAB;REDDY ANAND;NEWTON KENNETH JOSEPH;RUAN JU-AI |
分类号 |
H01L21/44 |
主分类号 |
H01L21/44 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|