| 摘要 |
A variable switching point inverter ( 30 ) is disclosed which lowers the threshold voltage lowered for both rising and falling edge input voltages (V<SUB>IN</SUB>) by changing the P/N ratio of the inverter based on the delayed output state (V<SUB>OUT</SUB>) of the inverter. The variable switching point inverter may be constructed as a CMOS integrated circuit with a first inverter stage ( 33, 34 ) coupled in parallel to a second inverter stage ( 35, 36 ) having extra PMOS ( 37 ) and NMOS ( 38 ) transistors connected to V<SUB>DD </SUB>and V<SUB>SS</SUB>, respectively, where the extra PMOS and NMOS transistors are controlled by the delayed output signal ( 40 ) generated by a delay element ( 39 ) coupled to the output of the first inverter stage. By using a delayed feed back signal ( 40 ) to control the extra PMOS and NMOS gates ( 37, 38 ), the switching point voltage of the first inverter stage ( 33, 34 ) is altered, depending on whether the input transitions are high-to-low or low-to-high.
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