发明名称 CLOCK MONITORING CIRCUIT, INFORMATION PROCESSING APPARATUS AND CLOCK MONITORING METHOD
摘要 <p>A check circuit (100) is provided in which in order to monitor clocks of an apparatus operating in synchronism with those clocks, units each performing a clock operation are divided into a plurality of functional or regional units, each of which includes a respective FF (10) performing a clock operation. The value of the FF (10) of the check circuit (100) is inverted at constant intervals and transmitted along a loop between one functional or regional unit and another. An error detecting circuit (20) checks whether the returned value of the FF (10) varies in a predetermined time period. If no change occurs in the predetermined time period, it is regarded as an error.</p>
申请公布号 WO2008026283(A1) 申请公布日期 2008.03.06
申请号 WO2006JP317220 申请日期 2006.08.31
申请人 FUJITSU LIMITED;SHIROTA, TOMOO;SANO, YOSHIHIKO 发明人 SHIROTA, TOMOO;SANO, YOSHIHIKO
分类号 G06F1/04;G06F11/30;H03K5/19;H04L7/00 主分类号 G06F1/04
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