METHOD AND STRUCTURE FOR IMPROVING DEVICE PERFORMANCE VARIATION IN DUAL STRESS LINER TECHNOLOGY

摘要

A method and semiconductor structure that overcome the dual stress liner boundary problem, without significantly increasing the overall size of the integrated circuit, are provided. In accordance with the present invention, the dual stress liner boundary (36) or gap therebetween is forced to land on a neighboring dummy gate region (14). By forcing the dual stress liner boundary or gap between the liners (30, 32) to land on the dummy gate region, the large stresses associated with the dual stress liner boundary (36) or gap are transferred to the dummy gate region, not the semiconductor substrate (12). Thus, the impact of the dual stress liner boundary on the nearest neighboring FET (16) is reduced. Additionally, benefits of device variability and packing density are achieved utilizing the present invention.