| 摘要 |
<p>A multi-port cache memory ( 200 ) comprising a plurality of input ports ( 201, 203 ) for inputting a plurality of addresses, at least part of each address indexing a plurality of ways; a plurality of output ports ( 227, 299 ) for outputting data associated with each of said plurality of addresses; a plurality of memory blocks ( 219 a , 219 b , 219 c) for storing said plurality of ways, each memory block comprising a single input port ( 217 a , 217 b , 217 c , 217 d) and storing said ways; means ( 209, 215, 223, 225 ) for selecting one of said plurality of ways such that data of said selected way is output on an associated output port ( 227, 229 ) of said cache memory ( 200 ); a predictor ( 211 ) for predicting which plurality of ways will be indexed by each of said plurality of addresses; and means ( 213 a , 213 b , 213 c , 213 d) for indexing said plurality of ways based on the predicted ways.</p> |
