发明名称
摘要 A method for design validation of complex IC with use of a combination of electronic design automation (EDA) tools and a design test station at high speed and low cost. The EDA tools and device simulator are linked to the event based test system to execute the original design simulation vectors and testbench and make modifications in the testbench and event based test vectors until satisfactory results are obtained. The event based test vectors are test vectors in an event format in which an event is any change in a signal which is described by its timing and the event based test system is a test system for testing an IC by utilizing the event based test vectors. Because EDA tools are linked with the event based test system, these modifications are captured to generate a final testbench that provides satisfactory results.
申请公布号 JP4058252(B2) 申请公布日期 2008.03.05
申请号 JP20010296263 申请日期 2001.09.27
申请人 发明人
分类号 G01R31/28;G06F17/50;G01R31/3183;G06F11/22;G06F11/26 主分类号 G01R31/28
代理机构 代理人
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