| 摘要 |
A number of architectural and implementation approaches are described for using extra path (Epath) storage that operate in conjunction with a compute register file to obtain increased instruction level parallelism that more flexibly addresses the requirements of high performance algorithms. A processor that supports a single load data to a register file operation can be doubled in load capability through the use of an extra path storage, an additional independently addressable data memory path, and instruction decode information that specifies two independently load data operations. By allowing the extra path storage to be accessible by arithmetic facilities, the increased data bandwidth can be fully utilized. In addition, flexible approaches to specifying the extra path storage, as a register, as a file, as a stack, as a tightly coupled input/output data interface path, and in conjunction with a scalable register file, can be implemented providing numerous options and capabilities for evolving processor designs.
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