发明名称 Circuit configuration and method for identifying error situations in interconnected systems
摘要 The circuit configuration according to the invention comprises an electrical signal line loop, several partial systems connected thereto, which evaluate the state of the signal line loop, wherein a first selectable switching means is looped in between a first end of the signal line loop and a first voltage connection and a second selectable switching means is looped in between a second end of the signal line loop and a second voltage connection, and a selection unit for selecting the first and second switching means. Use, e.g. in a fuel cell system.
申请公布号 US7340437(B2) 申请公布日期 2008.03.04
申请号 US20030528751 申请日期 2003.09.24
申请人 NUCELLSYS GMBH 发明人 ABERLE MARKUS;BEUTELSCHIESS KLAUS
分类号 G06F19/00;G01R31/00;G01R31/02;G01R31/28;G06F17/40 主分类号 G06F19/00
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