| 摘要 |
A display device disclosed herein prevents timing misalignment between signals of clock, data, and start pulses to be supplied to driver ICs. The display device comprises a controller, driver ICs and other components and each driver IC is configured to receive clock, data, and start pulses output from the controller, supply the received clock, data, and start pulses to a switch through parallel paths without routing the signals through its internal circuit, and supply the received clock, data, and start pulses to output terminals via the switch.
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