发明名称 Multiplexer
摘要 A multiplexer includes an encoder. The encoder includes: flip-flop circuits that output two signals having a transmission rate of B/2 at a frequency of B/2, while holding signals of each signal; an adder that adds the respective signals output from the flip-flop circuits and outputs the added signal; and a delay unit that delays the signal output from the flip-flop circuit by the time of 1/B, with respect to the signal output from the flip-flop circuit, and outputs the signal delayed to the adder.
申请公布号 US7340182(B2) 申请公布日期 2008.03.04
申请号 US20040471732 申请日期 2004.03.05
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 UEMURA ARITOMO;KOZAKI SEIJI;KUBO KAZUO;ICHIBANGASE HIROSHI
分类号 G02F1/01;H04B10/12;H04B10/04;H04B10/06;H04B10/14;H04B10/142;H04B10/152;H04B10/26;H04B10/28;H04J3/00;H04J3/04;H04J3/06;H04J14/00;H04J14/02;H04L5/14;H04L25/49;H04L25/497 主分类号 G02F1/01
代理机构 代理人
主权项
地址