发明名称 Test mode method and apparatus for internal memory timing signals
摘要 A method of testing internal signals of a memory for timing marginalities which may result in unstable operation includes: delaying internal address signals of the memory by an amount great enough so that data cannot be validly written to and read from memory locations which are accessed by address signals having timing marginalities which are delayed but small enough so that data can be validly written to and read from memory locations which are accessed by address signals not having such timing marginalities which are delayed. Data is then written to and read from memory locations which are accessed by delayed address signals, and a determination is made as to whether the data read from any memory location does not correspond with the data written to such memory location.
申请公布号 US7339841(B2) 申请公布日期 2008.03.04
申请号 US20050227099 申请日期 2005.09.16
申请人 INFINEON TECHNOLOGIES AG 发明人 VERSEN MARTIN;NIERLE KLAUS;KIEHL OLIVER;STAHL ERNST
分类号 G11C7/00 主分类号 G11C7/00
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