发明名称 Method and apparatus for generating layout pattern
摘要 A method includes: obtaining process technology definition data related to a process technology of each layer forming a basic cell, from a process technology definition file defining process technology definition data related to a process technology for use in fabricating a semiconductor integrated circuit, thereby holding a process technology definition table; obtaining device structure data including data related to a device template which defines a structure of each layer of the basic cell and data related to the structure of the layer defined in accordance with the device template, from a device structure definition file, thereby holding the obtained device structure data as a device structure definition table; and determining the structure of each layer defined in accordance with the device template held as the obtained device structure data, thereby generating the layout pattern of the basic cell forming the semiconductor integrated circuit.
申请公布号 US7340708(B2) 申请公布日期 2008.03.04
申请号 US20060362949 申请日期 2006.02.28
申请人 OKI ELECTRIC INDUSTRY CO., LTD. 发明人 HAMAZAKI RYOJI
分类号 G06F17/50 主分类号 G06F17/50
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