Analog-to-digital converter without track-and-hold

摘要

A system and method for converting an analog signal to a digital signal is provided. The analog to digital conversion is achieved without a dedicated sample-and-hold circuit. An ADC stage, preferably the front-end stage in the case of a pipeline ADC, samples the input voltage within a quantizer and within a residue generator. The sampling is performed with associated clocking signals and with switch capacitors also fulfilling the comparison with threshold voltages, within the quantizer and the generation of a residue signal within the residue generator.