| 摘要 |
A duty cycle correction circuit and a duty cycle correction method are provided to reduce current consumption and DCC(Duty Cycle Correction) time, by performing DCC operation by receiving a full swing signal when the full swing signal is inputted. A dividing part(100,300) outputs a first divided signal corresponding to a rising edge of an input clock signal and a second divided signal corresponding to a falling edge of the second divided signal by dividing the input clock signal inputted from the outside. A delay part(200,400) outputs a first and a second delay signal by delaying the first and the second divided signal according to a control signal. A clock generation part(500) generates an output clock signal with corrected duty by assembling the first and the second delay signal. A control part(600) outputs the control signal to control delay of the delay part by comparing high level period with low level period of the output clock signal.
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