SEMICONDUCTOR-ON-INSULATOR SRAM CONFIGURED USING PARTIALLY-DEPLETED AND FULLY-DEPLETED TRANSISTORS

摘要

SEMICONDUCTOR-ON-INSULATOR SRAM CONFIGURED USING PARTIALLY-DEPLETED AND FULLY-DEPLETED TRANSISTORS A static memory element includes a first inverter (P1 and N1) having an input coupled to a left bit node (114) and an output coupled to a right bit node (116). A second inverter (P2 and N2) has an input coupled to the right bit node (116) and an output coupled to the left bit node (114). A first fully depleted semiconductor-on-insulator transistor (110) has a drain coupled to the left bit node, and a second fully depleted semiconductor-on-insulator transistor (112) has a drain coupled to the right bit node.