发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT AND TESTING METHOD THEREOF
摘要 A semiconductor integrated circuit and a testing method thereof are provided to improve the reliability, by reducing test time of the semiconductor integrated circuit requiring a number of test items. A laser fuse circuit(125) memorizes a first trimming code by laser irradiation. An electric fuse circuit(126) memorizes a second trimming code by applying a voltage. An adjustment circuit adjusts potential level or timing according to the first or the second trimming code. A selector(127) selects the first trimming code memorized by the laser fuse circuit or the second trimming code memorized by the electric fuse circuit. The adjustment circuit adjusts the potential level or timing according to the first or the second trimming code selected by the selector.
申请公布号 KR20080018091(A) 申请公布日期 2008.02.27
申请号 KR20070052800 申请日期 2007.05.30
申请人 FUJITSU LIMITED 发明人 YAMAGUCHI SHUSAKU
分类号 G11C29/04;H01L21/82 主分类号 G11C29/04
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