Cryptographic logic circuits and method of performing logic operations

摘要

A cryptographic logic circuit, comprising: ```a first logic unit configured to execute at least one logic operation for a plurality of data pairs, the data pairs including random data and random masking data; and ```a second logic unit configured to execute a logic operation for the results of the first logic unit; ```wherein the first logic unit 201 includes: ```a first NAND gate 202 configured to execute a first logic NAND operation with first and second random masking data X', Y'; ```a second NAND gate 203 configured to execute a second logic NAND operation with the first random masking data X' and second random data S; ```a third NAND gate 204 configured to execute a third logic NAND operation with first random data R and the second random masking data Y'; and ```a fourth NAND gate 205 configured to execute a fourth logic NAND operation with the first and second random data R, S; ```and wherein the second logic unit 107 includes: ```a first XOR gate 108 configured to execute a first logic XOR operation with the output of the first NAND gate, the second NAND gate, and the second random masking data; and ```a second XOR gate 109 configured to execute a second logic XOR operation with the output of the third NAND gate, the fourth NAND gate operation, and the second random masking data. The cryptographic logic circuit may be a cryptographic AND (or NAND) logic circuit comprising a random masking scheme and having security against a power analysis attack.