PROCESSOR AND INTERFACE

摘要

The present invention relates to a processor which comprises an instruction set for execution on the processor, a processor architecture and a memory, wherein the instruction set and the processor architecture comprise characteristics which have been specifically tailored to ensure that the code density compiled for execution at least in part on the processor memory is relatively high. The invention -alsorelates-t?-a compiler.-The-invention-extends to a system comprising a master computer; one or more control pods; and one or more integrated circuits, each comprising one or more processors; wherein the master computer is operable to interact with any of said processors via said one or more control pods.