发明名称 |
False lock protection in a delay-locked loop (DLL) |
摘要 |
A delay-locked loop (DLL) to produce a plurality of delayed clock signals comprising combinational logic for false lock detection is provided. The combinational logic uses only a subset of the plurality of delayed clock signals to provide a forward indicator indicating a delay period (Deltat) is longer than a desired delay period. The combinational logic further provides a back indicator indicating the delay period (Deltat) is shorter than a desired delay period.
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申请公布号 |
US7336112(B1) |
申请公布日期 |
2008.02.26 |
申请号 |
US20060466078 |
申请日期 |
2006.08.21 |
申请人 |
HUAYA MICROELECTRONICS, LTD. |
发明人 |
SHA I-TEH;ZHANG LIFENG;SUN HAITAO;LI JINGRONG |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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