| 摘要 |
A sense amplifier circuit for sensing a logic state of a selected memory cell in a memory circuit includes a precharge circuit and a latch circuit. The precharge circuit is adapted for connection to a pair of complementary bit lines corresponding to the selected memory cell and is operative to selectively drive the pair of complementary bit lines to a first voltage in response to a first control signal. The latch circuit is adapted for connection to the pair of complementary bit lines. The sense amplifier circuit further includes a replication circuit adapted for connection to the pair of complementary bit lines. The replication circuit is operative to selectively transfer a voltage representative of a logic state on a first bit line of the pair of complementary bit lines to a second bit line of the pair of complementary bit lines in response to at least a second control signal.
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