| 摘要 |
A delay locked loop is provided to solve margin problem of a DLL(Delay Locked Loop) clock and data, by selecting delay time of an internal clock using a selection signal generated in a DLL-off mode. A buffering unit(100) outputs an internal clock by buffering an external clock. A control signal generation unit generates a control signal according to phase difference between the internal clock and an output clock of a delay model unit modeling delay elements of a clock path. A selection unit(700) outputs a selection signal to select delay time of the internal clock in response to a DLL-off mode signal. A delay unit delays the internal clock in response to the control signal or the selection signal. An output driver(600) drives an output signal of the delay unit.
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