发明名称 Structural regularity extraction and floorplanning in datapath circuits using vectors
摘要 In some embodiments, a computer-aided design system comprises a functional regularity extraction component, a structural regularity extraction component and a floorplanning component. The structural regularity extraction component provides a method to extract regularity for circuits (and in particular datapath circuits) based on the structural characteristics of a logic design. Some embodiments of the structural regularity extraction component automatically generate a set of vectors for the logic design. A vector is a group of template instances that are identical in function and in structure. The vectors generated by the structural regularity extraction component are used by a floorplanning component. The floorplanning component provides a method of generating a circuit layout from the set of vectors. In some embodiments, each vectors corresponds to a row in the circuit layout.
申请公布号 US7337418(B2) 申请公布日期 2008.02.26
申请号 US20030621253 申请日期 2003.07.14
申请人 INTEL CORPORATION 发明人 KALE SUDHAKAR;CHOWDHARY AMIT;SARIPELLA PHANI;SEHGAL NARESH K.;GUPTA RAJESH
分类号 G06F17/50;G06F9/45 主分类号 G06F17/50
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