Bistable circuit for e.g. hybrid latch flip-flop, has delay chain defining temporal window around pulse front of clock signal and comprising transistors for temporally adjusting duration of window during discharging of intermediate node

摘要

#CMT# #/CMT# The circuit has a PMOS transistor (P1) for pre-charging an intermediate node (M) of the circuit. A delay chain defines a temporal window around a pulse front of a clock signal (CLK). NMOS transistors (MN1-MN3) are controlled by an input data and discharge the intermediate node during duration of the temporal window. The delay chain has NMOS transistors (MND1-MND3) for temporally adjusting the duration of the window during discharging of the intermediate node. #CMT#USE : #/CMT# Bistable circuit for a latch and a flip-flop (all claimed) e.g. hybrid latch flip-flop. #CMT#ADVANTAGE : #/CMT# The transistors temporally adjust the duration of the window during discharge of the intermediate node, thus enabling the bistable circuit to be adapted to variations of transistor fabrication processes. #CMT#DESCRIPTION OF DRAWINGS : #/CMT# The drawing shows a circuit diagram of a master part of a hybrid latch flip-flop. CLK : Clock signal M : Intermediate node MN1-MN3, MND1-MND3 : NMOS transistors P1 : PMOS transistor Vdd : Power supply source.