| 摘要 |
It is possible to simplify the configuration of a circuit for controlling a variable delay circuit of a timing generator in real time and assure a timing margin (Eye aperture). The variable delay circuit (10) of the timing generator includes a delay circuit (11) having a plurality of clock buffers (13-1 to 13-n) connected longitudinally; a plurality of data buffers (15-11 to 15-nn) connected longitudinally, and data holding circuits (16-0 to 16-n) for outputting data to the data buffers (15-11 to 15-nn) in accordance with the clock from the delay circuit (11). The delay amount added to the data by the data buffers (15-11 to 15-nn) is made identical to the delay amount added to the clock by the clock buffers (13-1 to 13-n). |
