发明名称 DELAY ADJUSTING CIRCUIT AND ITS CONTROL METHOD
摘要 PROBLEM TO BE SOLVED: To provide a delay adjusting circuit which corrects a variation of delay characteristics owing to the variation of semiconductor elements on the same chip. SOLUTION: The delay adjusting circuit is provided with a delay portion, a first counter 10, a second counter 11 and a delay element adjusting portion. Nine steps of delay elements are connected in series in the delay portion. The first counter 10 detects whether the first edge of the rising edge of a seventh step signal of the delay portion is advanced more than the first reference signal edge of the rising edge of a first reference signal or not. The second counter 11 detects whether the second edge of the rising edge of a ninth step signal of the delay portion is delayed more than the first reference signal edge or not. The delay element adjusting portion outputs an output current Ib1 to adjust a delay time of the delay element of the delay portion by correcting a reference signal Vb so that the first edge is advanced more than the first reference signal edge in the first counter 10 and so that the second edge is delayed more than the first reference signal edge in the second counter 11. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008042708(A) 申请公布日期 2008.02.21
申请号 JP20060216587 申请日期 2006.08.09
申请人 FUJITSU LTD 发明人 ASANO SHIGETAKA
分类号 H03K5/13;H03L7/081 主分类号 H03K5/13
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