| 摘要 |
A data transmitting end utilizes a clock signal to transmit at least a data signal to a data receiving end. An adjustable delay compensation circuit for compensating data transmission delay between the data transmitting end and the data receiving end includes an adjustable delay circuit, a clock gating circuit, and at least a target signal generating circuit. The adjustable delay circuit is used for delaying the clock signal by a programmable delay amount to generate a target delay signal. The clock gating circuit is used for allowing the clock signal to reach the adjustable delay circuit when receiving a data transmission enabling signal. The target signal generating circuit is used for receiving the data signal and for sampling the data signal according to the target delay signal.
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