发明名称 Method and apparatus for decreasing layout area in a pipelined analog-to-digital converter
摘要 In accordance with one embodiment, there is provided a pipelined analog-to-digital converter (ADC) device. The pipelined ADC includes a first stage and a second stage. The first and second stages are configured to share a sub-ADC and a sub-digital-to-analog converter.
申请公布号 US2008042889(A1) 申请公布日期 2008.02.21
申请号 US20060506702 申请日期 2006.08.18
申请人 MICRON TECHNOLOGY, INC. 发明人 CHO TAEHEE
分类号 H03M1/38 主分类号 H03M1/38
代理机构 代理人
主权项
地址