| 摘要 |
A clock multiplier and a method for multiplying a clock are provided to prevent a difference between a phase and a frequency of an input clock and an output clock from being accumulated when multiplication ratio of the input clock is increased. A clock multiplier for multiplying a clock includes a phase frequency detector(310) creating first and second control signals according to a difference between a phase and a frequency of an input clock and a count signal. A clock selector(350) selects one of the input clock and a feedback clock in accordance with the input clock and the count signal. A voltage controlled delay line(340) controls a delay time of a signal selected according to a control voltage created in accordance with the first and second control signals. The phase frequency detector delays the input clock for a predetermined time, and creates the first and second control signals in accordance with a difference between a phase and a frequency of a delayed input clock and a delayed count signal.
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