| 摘要 |
A delayed locked loop (DLL) circuit is provided which includes a delay line for including a plurality of delay elements, and delaying an internal clock signal generated by buffering external clock signals by a first delay period, an internal delay for delaying an output signal of the delay line by a second delay period determined by modeling delay elements contained in a DRAM, and generating a feedback clock signal, a phase detector for generating an enable signal enabled when a phase difference between the feedback clock signal and a reference clock signal is contained in a predetermined period, and outputs the enable signal, a delay-period controller configured to generate, in response to the enable signal, first and second control signals for adjusting a counter output signal corresponding to at least one delay element selected from among the delay elements, a counter for receiving the first and second control signals, and generating a counter output signal corresponding to the at least one delay element, and a decoder for decoding the counter output signal, and generating the decoding signal, wherein the decoding signal indicates an enable state of the at least one delay element and adjusts the first delay period.
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