| 摘要 |
A semiconductor device in which capacitance per unit area can be enlarged without imposing any limitations upon layout has both a DRAM region and a logic region. The DRAM region and the logic region each have a plurality of cells provided with a respective capacitance element. Each capacitance element has an upper electrode, a lower electrode and a dielectric film sandwiched between the upper and lower electrodes. At least one of the upper electrode and lower electrode in the DRAM region is electrically isolated for every cell. In the logic region, the upper electrode, lower electrode and dielectric film are extended so as to be continuous from cell to cell of the plurality of cells.
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