摘要 |
<p>Disclosed herein is a hardware implementation for performing sequence alignment that preferably deploys a seed generation stage, an ungapped extension stage, and at least a portion of a gapped extension stage as a data processing pipeline on at least one hardware logic device. Hardware circuits for the seed generation stage, the ungapped extension stage, and the gapped extension stage are individually disclosed. In a preferred embodiment, the pipeline is arranged for performing BLASTP sequence alignment searching. Also, in a preferred embodiment, the at least one hardware logic device comprises at least one reconfigurable logic device such as an FPGA.</p> |
申请人 |
WASHINGTON UNIVERSITY;BECS TECHNOLOGY, INC.;CHAMBERLAIN, ROGER, DEAN;BUHLER, JEREMY, DANIEL;JACOB, ARPITH, CHACKO;LANCASTER, JOSEPH, MARION;HARRIS, BRANDON, BAXTER |
发明人 |
CHAMBERLAIN, ROGER, DEAN;BUHLER, JEREMY, DANIEL;JACOB, ARPITH, CHACKO;LANCASTER, JOSEPH, MARION;HARRIS, BRANDON, BAXTER |