TEST DEVICE AND TEST METHOD

摘要

Provided is a test device for testing a plurality of memories under test. The test device includes: a data supply unit for supplying test data in parallel to the test memories under test; a write control unit for writing the test data in parallel to the memories under test; and a read control unit for successively reading out the test data from each of the memories under test. The write control unit reads out memory block good/bad information in accordance with the write address from each of defective block storage units. When goo/bad information indicating that the memory block corresponding to the write address is defective is read from the defective block storage unit, the write control unit masks a write enable signal (WE) corresponding to the memory under test and inhibits write to the memory under test.