| 摘要 |
PROBLEM TO BE SOLVED: To increase a structure region of a bit line structure to take advantage of a chip area efficiently. SOLUTION: A plurality of bit line structures BL, a source shunt line structure SH1, and a dummy line structure SH2 are juxtaposed on the same layer at a predetermined width and at a predetermined interval; and a via plug structure Via2 is configured on the source shunt line structure SH1. COPYRIGHT: (C)2008,JPO&INPIT
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