BIT ORDERING FOR PACKETISED SERIAL DATA TRANSMISSION ON AN INTEGRATED CIRCUIT
摘要
<p>An on-chip integrated circuit interconnect (16) uses a serialization technique to divide a transaction to be transmitted into a sequence of transmission packets which are serially transmitted over a narrower connection. The order in which bits of the transaction are allocated to transmission packets is selected such that higher priority bits required by a receiving slave device in order that it can commence processing the transaction are sent first. This reduces the latency of the system.</p>
申请公布号
WO2008020149(A1)
申请公布日期
2008.02.21
申请号
WO2006GB03068
申请日期
2006.08.16
申请人
ARM LIMITED;MATHEWSON, BRUCE, JAMES;HARRIS, ANTHONY, JOHN