REDUCED PIN COUNT SCAN CHAIN IMPLEMENTATION

摘要

A synchronous logic device with reduced pin count scan chain includes more than two flip/flops (SDCO, SDC1, SDC2) coupled to form a shift register for receiving a scan data input signal (ScanDataln), a combinational logic circuit (20) for receiving device inputs, generating flip/flop inputs for the more than two flip/flops, and generating an output signal, a first multiplexer (MUX10) for providing a clock signal to the more than two flip/flops during a test mode, a second multiplexer (MUX12) for selecting between a test mode output from the shift register and the output signal from the combinational logic circuit (20), and for providing a scan data output signal (ScanDataOut).