JFET WITH BUILT IN BACK GATE IN EITHER SOI OR BULK SILICON

摘要

A Junction Field-Effect transistor with no surface contact for the back g ate and twice as much transconductance in the channel and with a higher swit ching speed is achieved by intentionally shorting the channel-well PN juncti on with the gate region. This is achieved by intentionally etching away fiel d oxide outside the active area at least in the gate region so as to expose the sidewalls of the active area down to the channel-well PN junction or a b uried gate which is in electrical contact with the well. Polysilicon is then deposited in the trench and doped heavily and an anneal step is used to dri ve impurities into the top and sidewalls of the channel region thereby creat ing a "wrap- around" gate region which reaches down the sidewalls of the cha nnel region to the channel-well PN junction. This causes the bias applied to the gate terminal to also be applied to the well thereby modulating the cha nnel transconductance with the depletion regions around both the gate-channe l PN junction and the channel-well PN junction.