| 摘要 |
PROBLEM TO BE SOLVED: To increase data read speed via an ECC circuit. SOLUTION: A semiconductor storage device includes: a memory cell array 11; a spare memory cell array 12; a spare data changeover circuit 13; a syndrome calculating circuit 14; and an error detecting/correcting circuit 15. Data of a memory cell replaced with the memory cell in the spare memory cell array is set to zero. The syndromes of the data D0, D1, D2 read out from the memory cell array are calculated. Data are switched to the data SD0, SD1, SD2 read out from the spare memory cell in parallel with the syndrome calculation, so as to calculate the syndrome of the data read out from the memory cell in the spare memory cell array. Calculated syndromes Sy0, Sy1, Sy2 and the output of the spare data changeover circuit are supplied to the error detecting/correcting circuit. Then, correction is performed when one bit error exists in the data read out from the memory cell array. COPYRIGHT: (C)2008,JPO&INPIT
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