| 摘要 |
An ETC(Electronic Toll Collection) terminal device updating additional functions, and an automatic collecting method using the same ETC terminal device are provided to enable a user to modify a program easily by designing a CPU and a modem as a VHDL(VHSIC Hardware Description Language) code. An ETC(Electronic Toll Collection) terminal comprises an RF receiving module and a CPU. The RF(Radio Frequency) receiving module(320) receives radio signals from a DSRC(Dedicated Short Range Communication) base station and transmits the signals to the CPU(Central Processing Unit). The CPU(310) composed by FPGA(Field-Programmable Gate Array), and performs accurate calculation of payment through the radio communication to the base station. The CPU comprises a processor(311), a DSRC modem block(312) and a user block(313). |
