| 摘要 |
A circuit which generates a dot clock synchronized to an external video signal which can ensure a pulse width allowed by a device which is supplied with the dot clock. A high frequency clock is divided to generate a first dot clock, and the phase is initialized in accordance with information on a previously set frequency division ratio upon detection of a significant edge of a horizontal synchronization signal. Also, a second dot clock, the logical level of which changes every minimum allowable period, is formed from the high frequency clock in accordance with information on a previously set minimum allowable period, and the phase is modified upon detection of the significant edge such that the minimum allowable period is ensured for the logical level period even before and after the detection. The second dot clock is selected upon detection of the significant edge, and afterwards, the first dot clock is selected when a confirmation can be made that the timing of the first dot clock is coincident with or behind the timing of the second dot clock.
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