| 摘要 |
Circuitry and methods for an efficient FIFO memory are provided. This efficient FIFO memory has two smaller standard single-port memory banks instead of one large dual-port memory bank, as in typical FIFO memories. Whereas the dual-port memory based FIFO memory can read and write data at the same time, a typical single-port memory based FIFO cannot. The operation of the two single-port memory banks are coordinated in order to provide similar or better performance than a dual-port memory based FIFO.
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